1. Field of the Invention
The present invention relates to a power on/off reset generator for use with digital logic and computer systems, and more specifically to a device for inhibiting such systems for write protection and protecting such systems from false interface signals while power is being sequenced.
2. Description of the Prior Art.
When power line interruptions occur or transient conditions exist, there may be loss of data or modification of data in memory in digital data systems. Some systems have utilized battery backup to prevent memory loss, but this procedure does not protect against the effect of power surges or transients. Some military systems may require control of the logic system only during turn on and turn off, referred to as a Class 3 system, while others require that reset siganl control be provided at all times, including the system power off condition, known as a Class 4 system.
Certain counters, registers and similar circuits in computers and other logic circuits must be initialized to a preselected state whenever the supply voltage has been below some minimum value, such as occurs when power is first turned on, or during primary power failures. The circuit which detects such minimum voltage levels and generates a reset signal which is utilized by the system to perform the required initialization is referred to as a Power On Reset (P.O.R.) Generator.
Typical prior art power on reset circuits have been described in the U.S. patent to Thomas, U.S. Pat. Nos. 4,296,338 and 4,096,560 to Footh. These circuits inhibit the controlled circuits upon return of power after an interruption, but do not allow inhibition under all power supply conditions. There is a need for a power on reset circuit design which will provide inhibition under all power supply conditions. A circuit is also needed that can be implemented using integrated circuit techniques.